In conventional processor architecture, caches of a Central Processing Unit (CPU) or Accelerated Processor Unit (APU) usually are embedded Static Random Access Memory (SRAM) in a System on Chip (SoC) device, or typically are an external SRAM chip for System in Package (SiP) devices. The SRAM architecture may be less efficient in terms of chip area and generally is more expensive than other memory architectures. Advanced technology nodes (e.g., below 20 nm nodes, such as 16 nm fin field effect transistor (FinFET) nodes and the like) may not offer embedded SRAM for SoC devices, such as due to the difficulty of manufacturing embedded SRAM in such nodes.